Microprocessor and Interfacing

Syllabus

UNIT –I

1. 8086 architecture- Functional Diagram, Register Organization, Memory segmentation, Memory addresses, physical memory organization, 2. Signal descriptions of 8086-common function signals, 3. Minimum and Maximum mode signals, 4. Read Write cycles, 5. Timing diagrams, 6. Interrupt structure of 8086.

UNIT – II

ASSEMBLY LANGUAGE PROGRAMMING OF 8086: 1. Instruction formats, addressing modes, instruction set, assembler directives, macros, 2. Simple programs involving logical, branch and call instructions, 3. Sorting, 4. evaluating arithmetic expressions, string manipulations.

UNIT – III

PERIPHERAL INTERFACING WITH 8086 MICROPROCESSOR: 1. 8255 PPI, 2. Keyboard, display controllers, Stepper motor, A/D & D/A Converter Interfacing with 8086 microprocessor. 3. Static and Dynamic memories, 4. Vector interrupt table, 5. Interrupt service routine, 6. Introduction to DOS & BIOS interrupts, 7. Programmable Interrupt Controller 8259, 8. DMA controller 8257, 9. Interfacing with 8086 microprocessor.

UNIT – IV

COMMUNICATION INTERFACE: 1. Serial communication standards, serial data transfer
schemes, 2. 8251USART architecture and Interfacing, RS-232, IEEE-488, 3. prototyping and trouble shooting.

UNIT – V

INTRODUCTION TO MICROCONTROLLERS: 1. Overview of 8051 microcontroller,
2. Architecture, 3. I/O ports and Memory organization, addressing modes and instruction set of 8051, 4. Simple programs.

What is a Microprocessor ?

A microprocessor is a small electronic device made on a single integrated circuit (IC) or chip. It acts as the brain of an electronic system and is responsible for processing data, executing instructions, and providing outputs. Microprocessors are a vital part of modern technology, found in computers, smartphones, and countless other devices.

Microprocessor performs three main functions: arithmetic operations, logical decision-making, and control tasks. It processes instructions and data, making decisions based on logic and controlling other components of the system. These tasks are handled efficiently because all the necessary components like the arithmetic logic unit (ALU), control unit, and registers are integrated into a single chip.

8-bit Processor – 8085 , Z80 , 6800

16-bit Processor – 8086 , 68000 , Z8000

32-bit Processor – 80386 , 80486


8086 Microprocessor

The 8086 microprocessor is divided into two main units:

  1. Bus Interface Unit (BIU):

    1. Handles communication with memory and I/O devices.
    2. Performs operations like fetching instructions, reading/writing data, and calculating physical addresses.
    3. Contains the Instruction Queue, Segment Registers, and Address Generation Logic.

  2. Execution Unit (EU):

    1. Executes instructions fetched by the BIU.
    2. Contains the Arithmetic and Logic Unit (ALU), General Purpose Registers, and Control Flags.

The 8086 microprocessor, introduced by Intel in 1978, is a 16-bit processor with a robust architecture that laid the foundation for modern microprocessor designs. Its architecture is capable of multitasking, memory management, and efficient peripheral interfacing. The processor operates with a 16-bit data bus and a 20-bit address bus, allowing it to address up to 1 MB of memory. The internal architecture is divided into two primary units: the Bus Interface Unit (BIU) and the Execution Unit (EU).

Functional Diagram

The functional diagram of the 8086 microprocessor illustrates its key components and their interactions. The BIU is responsible for generating physical addresses, fetching instructions, and interfacing with the external memory and I/O devices. It includes the segment registers, instruction pointer (IP), and an address generation mechanism. On the other hand, the EU decodes and executes instructions fetched by the BIU. It includes the general-purpose registers, arithmetic logic unit (ALU), flag register, and control circuitry.

  • Bus Interface Unit (BIU): This unit handles the processor's communication with memory and peripherals. It manages instruction fetching, operand fetching, and address calculation. The BIU also supports instruction queuing for efficient execution.

  • Execution Unit (EU): The EU takes instructions from the instruction queue, decodes them, and executes them. It performs arithmetic, logic, and control operations using the ALU and control circuitry.

Register Organization

The 8086 microprocessor has 14 registers, each 16 bits wide. These are categorized as follows:

  • General-Purpose Registers: AX, BX, CX, and DX. Each register can be divided into two 8-bit registers (e.g., AH and AL for AX). These are used for arithmetic operations, data storage, and data transfer.

  • Segment Registers: The CS (Code Segment), DS (Data Segment), SS (Stack Segment), and ES (Extra Segment) registers define the memory segments used for code, data, stack, and additional data storage, respectively.

  • Pointer and Index Registers: The SP (Stack Pointer), BP (Base Pointer), SI (Source Index), and DI (Destination Index) are used for addressing memory and stack operations.

  • Instruction Pointer (IP): This register holds the address of the next instruction to be executed.

  • Flag Register: It indicates the state of the processor and results of operations, with flags such as Zero Flag, Carry Flag, Sign Flag, and Overflow Flag.

Memory Segmentation

The memory segmentation feature of the 8086 allows its 1 MB addressable memory to be divided into segments of 64 KB each. This segmentation facilitates modular programming, simplifies memory management, and allows efficient data access. Four segments are defined:

  1. Code Segment (CS): Stores executable instructions.

  2. Data Segment (DS): Contains program data.

  3. Stack Segment (SS): Used for stack operations like push and pop.

  4. Extra Segment (ES): Provides additional storage for data.

Memory Addresses

Physical memory addresses are calculated by combining a segment base address with an offset. 

This addressing mechanism enables access to a large memory space using a 16-bit segment and a 16-bit offset.

Physical Memory Organization

The 8086 organizes memory into overlapping segments, allowing efficient program execution and data handling. Each segment can store up to 64 KB of data or code. The overlapping nature of segments ensures that memory is utilized optimally.

Signal Descriptions of 8086

The 8086 microprocessor has various signals categorized into common function signals, minimum mode signals, and maximum mode signals. These signals control the processor’s operations and interactions with external devices.

  • Common Function Signals: These include:

  • AD0-AD15: Multiplexed address and data bus.

  • A16-A19/S3-S6: Address/status lines.
  • RD: Read control signal.
  • WR: Write control signal.
  • ALE: Address Latch Enable.
  • INTR/INTA: Interrupt request and acknowledge signals.
  • Minimum and Maximum Mode Signals

The 8086 can operate in two modes:

  • Minimum Mode: Used in single-processor systems. Signals include HOLD, HLDA, and RDY for bus control.

  • Maximum Mode: Used in multiprocessor systems. Signals include S2, S1, S0 (status lines), LOCK (bus lock signal), and RQ/GT1, RQ/GT0 (bus request/grant).

Read and Write Cycles

The read and write cycles describe the sequence of operations the processor performs to read from or write to memory and I/O devices. Each cycle involves address generation, data transfer, and signal activation. Key steps in a read cycle include:

  1. Address placement on the bus.

  2. Activation of the RD signal.

  3. Data transfer from memory to the processor.

In a write cycle, data flows from the processor to memory or an I/O device, accompanied by the WR signal.

Timing Diagrams

Timing diagrams represent the chronological order of signal changes during read/write cycles. They provide a visual depiction of the relationship between address, data, and control signals. For example, the diagram for a read cycle shows:

  • Address and data buses transitioning to valid states.

  • Activation and deactivation of ALE, RD, and other control signals.

  • Timing of data availability on the data bus.

Interrupt Structure

The interrupt system of the 8086 enhances its ability to handle asynchronous events. It supports 256 software and hardware interrupts, which are managed through an Interrupt Vector Table (IVT). Key features include:

  • Interrupt Types: Hardware interrupts (e.g., INTR, NMI) and software interrupts (e.g., INT instructions).

  • Priority Levels: Non-maskable interrupts (NMI) have the highest priority.

  • Interrupt Service Routine (ISR): A special routine executed when an interrupt occurs.

The interrupt structure ensures that the processor can respond to critical events promptly while maintaining efficient execution of the main program.




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